Publisher
Springer International Publishing
Reference24 articles.
1. R. Poujois, B. Baylac, D. Barbier, J. Ittel, Low-level MOS transistor amplifier using storage techniques, in IEEE International Solid-State Circuits Conference, Digest of Technical Papers (1973), pp. 152–153
2. C.C. Enz, G.C. Temes, Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization. Proc. IEEE 84, 1584–1614 (1996)
3. W. Liu, Y. Chang, S.-K. Hsien et al., A 600mW 30mW 0.13μm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization, in International Solid-State Circuits Conference, Digest of Technical Papers (2009), pp. 82–83
4. J. Li, U.-K. Moon, Background calibration techniques for multistage pipelined ADCs with digital redundancy. IEEE Trans. Circuits Syst. II 50, 531–538 (2003)
5. J. McNeill et al., Split ADC’ architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC. IEEE J. Solid State Circuits 40, 2437–2445 (2005)