1. Barkalov A, Titarenko L, Chmielewski S (2007) Optimization of logic circuit of Moore FSM on CPLD. Pomiary Autom Kontrola 53(5):18–20
2. Barkalov A, Titarenko L, Chmielewski S (2007) Optimization of Moore FSM on CPLD. In: Proceedings of the sixth international conference CAD DD’07, vol 2. Minsk, pp 39–45
3. Barkalov A, Titarenko L, Chmielewski S (2007) Optimization of Moore FSM on system-on chip. In: Proceedings of IEEE east-west design and test symposium – EWDTS’07. Yerevan, Armenia, Kharkov, pp 105–109
4. Barkalov A, Titarenko L, Kołopeńczyk M (2006) Optimization of control unit with code sharing. In: Proceedings of the 3rd international workshop of IFAC discrete–event system design (DESDES’06), Rydzyna, 2006. University of Zielona Góra Press, pp 195–200
5. Barkalov A, Węgrzyn M (2006) Design of control units with programmable logic. University of Zielona Góra Press