Development and Performances Comparison of Memory Architectures for Multiprocessor System on Chip at the SystemC/TLM
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-26852-6_71
Reference21 articles.
1. Aamali, K., Alali, A., Sadik, M., El Hariti, Z.: A review of the different levels of abstraction for systems-on-chip (SoC). E3S Web Conf. 229, 01025 (2021). https://doi.org/10.1051/e3sconf/202122901025
2. Aamali, K., Sadik, M., Alali, A., Hariti, Z.E.: Literary study of memory architectures for multiprocessor system on chip (MPSoC). JARDCS 11, 1067–1071 (2019). https://doi.org/10.5373/JARDCS/V11SP11/20193138
3. Ackland, B., et al.: A Single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP. J. Solid State Circuit. 35, 412–424 (2000)
4. Aguilar, M.A., Leupers, R., Ascheid, G., Murillo, L.G.: Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs. In: Proceedings of the 53rd Annual Design Automation Conference, pp 1–6. ACM, Austin Texas (2016)
5. Alali, A., Assayad, I., Sadik, M.: Modeling and simulation of multiprocessor systems MPSoC by SystemC/TLM2 (2014). arXiv:14080982
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