A Digitally Controlled Delay Generator Implemented with Cyclone V FPGA Using Timing Analysis
Author:
Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-31007-2_4
Reference9 articles.
1. Song, Y., Liang, H., Zhou, L., Du, J., Ma, J., Yue, Z.: Large dynamic range high resolution digital delay generator based on FPGA. In: 2011 International Conference on Electronics, Communications and Control (ICECC), pp. 2116–2118. IEEE (2011)
2. Cui, K., Li, X., Zhu, R.: A high-resolution programmable Vernier delay generator based on carry chains in FPGA. Rev. Sci. Instrum. 88(6), 064703 (2017)
3. Li, J., Zheng, Z., Liu, M., Wu, S.: Large dynamic range accurate digitally programmable delay line with 250-ps resolution. In: 2006 8th International Conference on Signal Processing. IEEE (2006)
4. Giordano, R., Ameli, F., Bifulco, P.: High-resolution synthesizable digitally-controlled delay lines. IEEE Trans Nucl. Sci. 62(6), 3163–3171 (2015)
5. Cheng, X., Song, R., Xie, G., Zhang, Y., Zhang, Z.: A new FPGA-based segmented delay-line DPWM with compensation for critical path delays. IEEE Trans. Power Electron. 33, 10794–10802 (2017)
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