Design of 14-Bit SAR ADC with Improved Linearity and Signal Dependent Charge Re-Cycling
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-030-03146-6_88
Reference17 articles.
1. Lin, Jin.-Yi., Hsieh, Chih.-Cheng.: A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 62(1), 70–79 (2015)
2. Tai, H.-Y., Hu, Y.-S., Chen, H.-W., Chen, H.-S.: 11.2 A 0.85 fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40 nm CMOS. In: 2014 IEEE International on Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 196–197. IEEE (2014)
3. Scott, Michael.D., Boser, Bernhard.E., Pister, Kristofer.S.J.: An ultralow-energy ADC for smart dust. IEEE J. Solid-State Circuits 38(7), 1123–1129 (2003)
4. Verma, Naveen., Chandrakasan, Anantha.P.: An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes. IEEE J. Solid-State Circuits 42(6), 1196–1205 (2007)
5. Mortezapour, Siamak., Lee, Edward.K.F.: A 1-V, 8-bit successive approximation ADC in standard CMOS process. IEEE J. Solid-State Circuits 35(4), 642–646 (2000)
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