1. Sumitra, V., Sivakumar, R., & Ko, S.-B. (2019). An improved low-power coding for serial network-on-chip links. Circuits, Systems, and Signal Processing, 39, 1896–1919.
2. Jan, C.-H., Bhattacharya, U., Brain, R., Choi, S.-J., Curello, G., Gupta, G., et al. (2012). A 22 nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra-low power, high performance and high density SoC applications. In International Electron Devices Meeting Technical Digest (pp. 44–47).
3. International Roadmap for Semiconductors (ITRS). https://www.ITRS.net. Accessed on June 20, 2020.
4. Guerrier, P., & Greiner, A. (2000). A generic architecture for on-chip packet-switched interconnections. In Proceedings of the Conference on Design, Automation and Test in Europe (pp. 250–256), March 27–30, Paris, France.
5. Duato, J., Yalamanchili, S., & Ni, L. (1997).Interconnection networks: An engineering approach. Los Alamitos, CA: IEEE CS Press.