Memory Access Pattern-Aware DRAM Controller Design for Mixed-Criticality Systems
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-030-17910-6_3
Reference21 articles.
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2. Burns, A., Davis, R.: Mixed criticality systems-a review. Department of Computer Science, University of York, Technical Reports (2013)
3. Ecco, L., Tobuschat, S., Saidi, S., Ernst, R.: A mixed critical memory controller using bank privatization and fixed priority scheduling. In: 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, pp. 1–10, August 2014. https://doi.org/10.1109/RTCSA.2014.6910550
4. Goossens, S., Kuijsten, J., Akesson, B., Goossens, K.: A reconfigurable real-time sdram controller for mixed time-criticality systems. In: 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 1–10, September 2013. https://doi.org/10.1109/CODES-ISSS.2013.6658989
5. Henning, J.L.: SPEC CPU2006 benchmark descriptions. SIGARCH Comput. Archit. News 34(4), 1–17 (2006). https://doi.org/10.1145/1186736.1186737
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