Graph-Based Code Restructuring Targeting HLS for FPGAs-Reference-Cited by-同舟云学术

Graph-Based Code Restructuring Targeting HLS for FPGAs

Published:2019 Issue: Volume: Page:230-244
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Ferreira Afonso Canas^ORCID,Cardoso João M. P.^ORCID

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-030-17227-5_17

Reference18 articles.

1. Nane, R., et al.: A survey and evaluation of FPGA high-level synthesis tools. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 35(10), 1591–1604 (2016)

2. Cardoso, J.M.P., Weinhardt, M.: High-level synthesis. In: Koch, D., Hannig, F., Ziener, D. (eds.) FPGAs for Software Programmers, pp. 23–47. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-26408-0_2

3. Ferreira, A.C., Cardoso, J.M.P.: Unfolding and folding: a new approach for code restructuring targeting HLS for FPGAs. In: FSP Workshop 2018: Fifth International Workshop on FPGAs for Software Programmers, Dublin, Ireland, pp. 1–10 (2018)

4. Tsoutsouras, V., et al.: An exploration framework for efficient high-level synthesis of support vector machines: case study on ECG arrhythmia detection for Xilinx Zynq SoC. J. Sig. Process. Syst. 88(2), 127–147 (2017)

5. Texas Instrument, TMS320C6000 DSP Library (DSPLIB). Accessed 16 June 2018. http://www.ti.com/tool/sprc265

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