Hardware Realization of Montgomery Multiplication with Radix-2
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-030-74524-0_7
Reference21 articles.
1. Han J, Wang S, Huang W, Yu Z, Zeng X (2013) Parallelization of radix-2 Montgomery multiplication on multicore platform. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(12):2325–2330
2. Hariri A, Reyhani-Masoleh A (2009) Bit-serial and bit-parallel Montgomery multiplication and squaring over GF (2m). IEEE Trans Comput 58(10):1332–1345
3. Harris D, Krishnamurthy R, Anders M, Mathew S, Hsu S (2005) An improved unified scalable radix-2 Montgomery multiplier. In: 17th IEEE symposium on computer arithmetic (ARITH’05). IEEE, pp 172–178
4. Huang M, Gaj K, El-Ghazawi T (2010) New hardware architectures for Montgomery modular multiplication algorithm. IEEE Trans Comput 60(7):923–936
5. Huang M, Gaj K, Kwon S, El-Ghazawi T (2008) An optimized hardware architecture for the Montgomery multiplication algorithm. In: International workshop on public key cryptography. Springer, pp 214–228
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