Large-Scale Circuit Performance Modeling by Bayesian Model Fusion-Reference-Cited by-同舟云学术

Large-Scale Circuit Performance Modeling by Bayesian Model Fusion

Published:2019 Issue: Volume: Page:403-422
ISSN:
Container-title:Machine Learning in VLSI Computer-Aided Design
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Author:

Tao Jun,Wang Fa,Cachecho Paolo,Zhang Wangyang,Sun Shupeng,Li Xin,Kanj Rouwaida,Gu Chenjie,Zeng Xuan

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-030-04666-8_14

Reference37 articles.

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2. X. Li, J. Le, L. Pileggi, Statistical Performance Modeling and Optimization (Now Publishers, Hanover, 2007)

3. Semiconductor Industry Associate, International Technology Roadmap for Semiconductors (Semiconductor Industry Association, Washington, 2011)

4. R. Rutenbar, G. Georges, J. Roychowdhury, Hierarchical modeling, optimization and synthesis for system-level analog and RF designs. Proc. IEEE 95(3), 640–669 (2007)

5. A. Tang, F. Hsiao, D. Murphy, I. Ku, J. Liu, S. D’Souza, N. Wang, H. Wu, Y. Wang, M. Tang, G. Virbila, M. Pham, D. Yang, Q. Gu, Y. Wu, Y. Kuan, C. Chien, M. Chang, A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip, in IEEE International Solid-State Circuits Conference (2012), pp. 316–318

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