Author:
Tehranipoor Mark,Zamiri Azar Kimia,Asadizanjani Navid,Rahman Fahim,Mardani Kamali Hadi,Farahmandi Farimah
Publisher
Springer Nature Switzerland
Reference98 articles.
1. A. Nahiyan, K. Xiao, K. Yang, Y. Jin, D. Forte, M. Tehranipoor, AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs, in 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) (2016), pp. 1–6. https://doi.org/10.1145/2897937.2897992
2. G.K. Contreras, A. Nahiyan, S. Bhunia, D. Forte, M. Tehranipoor, Security vulnerability analysis of design-for-test exploits for asset protection in SoCs, in 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) (IEEE, 2017), pp. 617–622
3. P. Mishra, M. Tehranipoor, S. Bhunia, Security and trust vulnerabilities in third-party IPs, in Hardware IP Security and Trust (Springer, Berlin, 2017), pp. 3–14
4. J. Lee, M. Tebranipoor, J. Plusquellic, A low-cost solution for protecting IPs against scan-based side-channel attacks, in 24th IEEE VLSI Test Symposium (IEEE, 2006), 6 pp.
5. N. Pundir, J. Park, F. Farahmandi, M. Tehranipoor, Power side-channel leakage assessment framework at register-transfer level. IEEE Trans. Very Large Scale Integr. Syst. 30(9), 1207–1218 (2022)