Author:
Sisejkovic Dominik,Leupers Rainer
Publisher
Springer International Publishing
Reference7 articles.
1. D. Šišejković, F. Merchant, L.M. Reimann, R. Leupers, S. Kegreiß, Scaling logic locking schemes to multi-module hardware designs, in Architecture of Computing Systems—ARCS 2020, ed. by A. Brinkmann, W. Karl, S. Lankes, S. Tomforde, T. Pionteck, C. Trinitis (Springer, Cham, 2020), pp. 138–152
2. Synopsys Inc., ASIP designer. https://www.synopsys.com/dw/ipdir.php?ds=asip-designer
3. Synopsys Inc., Design compiler. https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test/dc-ultra.html
4. Synopsys Inc., Formality. https://www.synopsys.com/verification.html
5. S. Takamaeda-Yamazaki, Pyverilog: a python-based hardware design processing toolkit for verilog HDL, in Applied Reconfigurable Computing, ed. by K. Sano, D. Soudris, M. Hübner, P.C. Diniz (Springer, Cham, 2015), pp. 451–460