1. Chen, S., Postula, A., Jozwiak, L.: Synthesis of XOR storage schemes with different cost for minimization of memory contention. In: 1999 Proceedings of the Euromicro Conference, vol. 1, pp. 170–177. IEEE (1999)
2. IFIP — The International Federation for Information Processing;RW Hartenstein,1997
3. Aho, E., Vanne, J., Kuusilinna, K., et al.: Address computation in configurable parallel memory architecture. IEICE Trans. Inf. Syst. 87-D(7), 1674–1681 (2004)
4. Takala, J., Jarvinen, T.: Stride permutation access in interleaved memory systems (2003)
5. Budnik, P., Kuck, D.J.: The organization and use of parallel memories. IEEE Trans. Comput. 20(12), 1566–1569 (1971)