Design of Energy Efficient ALU Using Clock Gating for a Sensor Node
Author:
Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-030-23162-0_35
Reference15 articles.
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3. Hemapriya, K., Karthikeyan, R.: Low-power folded tree architecture and multi-bit flip-flop merging technique for WSN nodes. In: International Conference on Information Communication and Embedded Systems, p. 978-1-4799-3834 (2014)
4. Ranjithkumar, K., Anandharajan, T.R.V.: DSP architecture with folded tree for power constraint devices. In: Sixth International Conference on Advanced Computing (ICoAC), p. 978-1-4799-81S9 (2014)
5. Le, D.-H., Sugii, N., Kamohara, S., Nguyen, X.-T., Ishibashi, K., Pham, C.-K.: Design of a Low-power fixed-point 16-bit digital signal processor using 65 nm SOTB process. In: 2015 International Conference on IC Design & Technology (ICICDT) (2015)
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