Publisher
Springer International Publishing
Reference50 articles.
1. N. Lourenço, R. Martins, N. Horta, Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects (Springer, 2017)
2. Cadence, Virtuoso Analog Design Environment GXL [Online]. Available:
http://www.cadence.com
. Accessed 15 May 2019
3. MunEDA, WIKED™ [Online]. Available:
http://www.muneda.com
. Accessed am 15 May 2019
4. R. Martins, N. Lourenco, N. Horta, J. Yin, P.-I. Mak, R.P. Martins, “Many-objective sizing optimization of a class-C/D VCO for ultralow-power IoT and ultralow-phase-noise cellular applications. IEEE Trans. Very Large Scale Integr. Syst. 27(1), 69–82 (2019)
5. F. Passos et al., A multilevel bottom-up optimization methodology for the automated synthesis of RF systems. IEEE Trans. Comput. Des. Integr. Circ. Syst. (2019).
https://doi.org/10.1109/TCAD.2018.2890528