Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators-Reference-Cited by-同舟云学术

Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators

Published:2021 Issue: Volume: Page:81-92
ISSN:0302-9743
Container-title:Applied Reconfigurable Computing. Architectures, Tools, and Applications
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Author:

Heinz Carsten^ORCID,Koch Andreas^ORCID

Publisher

Springer International Publishing

Link

https://link.springer.com/content/pdf/10.1007/978-3-030-79025-7_6

Reference10 articles.

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2. Chen, T., Srinath, S., Batten, C., Suh, G.E.: An architectural framework for accelerating dynamic parallel algorithms on reconfigurable hardware. In: 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 55–67. IEEE (2018)

3. Dubucq, T., Forlini, T., Dos Reis, V.L., Santos, I.: Matrix: bench - benchmarking the state-of-the-art task execution frameworks of many-task computing (2015)

4. Ernsting, S., Kuchen, H.: A scalable farm skeleton for hybrid parallel and distributed programming. Int. J. Parallel Program. 42(6), 968–987 (2014). https://doi.org/10.1007/s10766-013-0269-2

5. Heinz, C., Hofmann, J.A., Sommer, L., Koch, A.: Improving job launch rates in the TaPaSCo FPGA middleware by hardware/software-co-design. In: 2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS), pp. 22–30 (2020). https://doi.org/10.1109/ROSS51935.2020.00008

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