Hardware Level Approximations
Author:
Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-030-94705-7_3
Reference147 articles.
1. Zhang, H., Putic, M., & Lach, J. (2014). Low power GPGPU computation with imprecise hardware. In The 51st Annual Design Automation Conference 2014, DAC ’14, San Francisco, CA, June 1–5, 2014 (pp. 99:1–99:6). ACM.
2. Grigorian, B., Farahpour, N., & Reinman, G. (2015). BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing. In 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA, February 7–11, 2015 (pp. 615–626). IEEE Computer Society.
3. Karakonstantis, G., Banerjee, N., & Roy, K. (2010). Process-variation resilient and voltage-scalable DCT architecture for robust low-power computing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(10), 1461–1470.
4. Karakonstantis, G., Chatterjee, A., & Roy, K. (2011). Containing the nanometer “pandora-box”: Cross-layer design techniques for variation aware low power systems. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 1(1), 19–29.
5. Esmaeilzadeh, H., Sampson, A., Ceze, L., & Burger, D. (2012). Architecture support for disciplined approximate programming. In T. Harris & M. L. Scott (Eds.), Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2012, London, March 3–7, 2012 (pp. 301–312). ACM.
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