Content-Addressable Memories
Author:
Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-030-55119-3_6
Reference24 articles.
1. Supreet Jeloka, Naveen Akesh, Dennis Sylvester, and David Blaauw. A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell. In VLSI Circuits (VLSI Circuits), 2015 Symposium on, pages C272–C273. IEEE, 2015.
2. Toshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, Yasuhisa Takeyama, Tsuyoshi Midorikawa, Kenji Hashimoto, Ichiro Wakiyama, Shinji Miyano, and Takehiko Hojo. A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, pages 236–237. IEEE, 2014.
3. Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, and Ching-Te Chuang. Single-ended subthreshold SRAM with asymmetrical write/read-assist. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(12):3039–3047, 2010.
4. Richard F Hobson. A new single-ended SRAM cell with write-assist. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(2):173–181, 2007.
5. Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, and Costin Anghel. 1.56 GHz/0.9 V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell. In ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, pages 316–319. IEEE, 2017.
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