1. Accellera Systems Initiative, Core SystemC Language and Examples.
http://accellera.org/downloads/standards/systemc
2. Center for Embedded and Cyber-physical Systems, Recoding Infrastructure for SystemC (RISC).
http://www.cecs.uci.edu/~doemer/risc.html
3. Center for Embedded and Cyber-physical Systems, RISC Docker Container.
https://hub.docker.com/r/ucirvinelecs/risc050/
4. Center for Embedded and Cyber-physical Systems, RISC Release version 0.5.0.
http://www.cecs.uci.edu/~doemer/risc.html#RISC050
5. W. Chen, X. Han, R. Dömer, Multi-core simulation of transaction level models using the system-on-chip environment. IEEE Des. Test Comput. 28(3), 20–31 (2011)