Learning Based Timing Closure on Relative Timed Design
Author:
Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-030-81641-4_7
Reference21 articles.
1. Nair, R., Berman, C.L., Hauge, P.S., Yoffa, E.J.: Generation of performance constraints for layout. IEEE Trans. Comput. Aided Des. 8(8), 860–874 (1989)
2. Stevens, K.S., Ginosar, R., Rotem, S.: Relative timing. IEEE Trans. Very Large Scale Integr. Syst. 1(11), 129–140 (2003)
3. Manoranjan, J.V., Stevens, K.S.: Qualifying relative timing constraints for asynchronous circuits. in: International Symposium on Asynchronous Circuits and Systems, pp. 91–98 (2016)
4. Sharma, T., Stevens, K.S.: Physical design variation in relative timed asynchronous circuits. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 278–283 (2017)
5. Sharma, T., Stevens, K.S.: Automatic timing closure for relative timed designs. In: 28th IFIP International Conference on Very Large Scale Integration, IEEE (2020)
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