3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-030-81641-4_14
Reference19 articles.
1. Larrieu, G., Han, X.-L.: Vertical nanowire array-based field effect transistors for ultimate scaling. Nanoscale 5, 2437 (2013). https://doi.org/10.1039/c3nr33738c
2. Guerfi, Y., Larrieu, G.: Vertical silicon nanowire field effect transistors with nanoscale gate-all-around. Nanoscale Res. Lett. 11, 210 (2016). https://doi.org/10.1186/s11671-016-1396-7
3. Hamza, A., Imail, R., Alias, N.E., Peng Tan, M.L., Poorasl, A.: Explicit continuous models of drain current, terminal charges and intrinsic capacitance for a long-channel junctionless nanowire transistor. Phys. Scr. 94, 105813 (2019)
4. Lime, F., Moldovan, O., Iniguez, B.: A compact explicit model for long-channel gate-all-around junctionless MOSFETs. Part I: DC characteristics. IEEE Trans. Electron Devices 61, 3036–3041 (2014). https://doi.org/10.1109/TED.2014.2340441
5. Mukherjee, C., Larrieu, G., Maneux, C.: Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors. In: EUROSOI ULIS (2020)
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