3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-030-81641-4_13
Reference27 articles.
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2. Colinge, J.P.: FinFETs and Other Multi-Gate Transistors, 1st edn. Springer, Boston (2007). https://doi.org/10.1007/978-0-387-71752-4
3. Yoon, S.W., Yang, D.W., Koo, J.H., Padmanathan, M., Carson, F.: 3D TSV processes and its assembly/packaging technology. In: 2009 IEEE International Conference on 3D System Integration, San Francisco, CA, pp. 1–5 (2009). https://doi.org/10.1109/3DIC.2009.5306535
4. Chua, T.T., et al.: 3D interconnection process development and integration with low stress TSV. In: 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, pp. 798–802 (2010). https://doi.org/10.1109/ECTC.2010.5490728
5. Van Olmen, J., et al.: 3D stacked IC demonstration using a through silicon via first approach. In: 2008 IEEE International Electron Devices Meeting, San Francisco, CA, pp. 1–4 (2008). https://doi.org/10.1109/IEDM.2008.4796763
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