Leakage Current Reduction Techniques Using Current Mode Logic Circuits

Author:

Jyotsna K. A.,Satish Kumar P.,Madhavi B. K.

Publisher

Springer International Publishing

Reference10 articles.

1. Tajalli SA, Braurer EJ, Leblebici Y, Vittoz E (2008) Sub threshold source coupled logic circuits for ultra-low-power applications. IEEE J Solid-State Circuits 43(7):1699–1710

2. Tajalli SA, Vittoz E, Braurer EJ, Leblebici Y (2007) Ultra-low power sub threshold current mode logic utilizing PMOS load device. Electron Lett 43(17):911–913

3. Tajalli SA, Leblebici Y (2007) Leakage current reduction using sub threshold source coupled logic. IEEE Trans Circuits Syst -2: Express Briefs, 56(5):374–378

4. Roy S, Myrad M, Nipun K (2011) Understanding sub threshold source coupled logic for ultra low power applications, Master thesis, Linkoping University, Sweden

5. Parshionikar S, Bhoir DV (2013) Standby leakage power reduction techniques in deep sub micron CMOS VLSI circuits. Int J Comput Appl 0975:8887. International Conference on Communication Technology

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