Performance Evaluation of Various RISC Processor Systems: A Case Study on ARM, MIPS and RISC-V

Author:

Liu Yu,Ye Kejiang,Xu Cheng-Zhong

Publisher

Springer International Publishing

Reference24 articles.

1. Seal, D.: ARM Architecture Reference Manual. Pearson Education, London (2001)

2. Hennessy, J., et al.: MIPS: a microprocessor architecture. ACM SIGMICRO Newslett. 13(4), 17–22 (1982)

3. Asanović, K., Patterson, D.A.: Instruction sets should be free: the case for RISC-V. EECS Department, University of California, Berkeley, Technical Report. UCB/EECS-2014-146, 2014

4. Greengard, S.: Will RISC-V revolutionize computing? Commun. ACM 63(5), 30–32 (2020)

5. Lee, Y., et al.: An agile approach to building RISC-V microprocessors. IEEE Micro 36(2), 8–20 (2016)

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