A Multi-step Approach for Identifying Unknown Defect Patterns on Wafer Bin Map
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-58113-7_18
Reference14 articles.
1. Hsu, C.Y., Chen, W.J., Chien, J.C.: Similarity matching of wafer bin maps for manufacturing intelligence to empower Industry 3.5 for semiconductor manufacturing. Comput. Ind. Eng. 142, 106358 (2020). https://doi.org/10.1016/j.cie.2020.106358
2. Chen, S., Zhang, Y., Hou, X., Shang, Y., Yang, P.: Wafer map failure pattern recognition based on deep convolutional neural network. Expert Syst. Appl. 209, 118254 (2022). https://doi.org/10.1016/j.eswa.2022.118254
3. Hansen, C.K., Thyregodb, P.: Use of wafer maps in integrated circuit manufacturing. Microelectron. Reliab. 38(6–8), 1155–1164 (1998)
4. Hansen, M.H., Nair, V.N., Friedman, D.J.: Monitoring wafer map data from integrated circuit fabrication processes for spatially clustered defects. Technometrics 39(3), 241–253 (1997)
5. Tello, G., Al-Jarrah, O.Y., Yoo, P.D., Al-Hammadi, Y., Muhaidat, S., Lee, U.: Deep-structured machine learning model for the recognition of mixed-defect patterns in semiconductor fabrication processes. IEEE Trans. Semicond. Manuf. 31(2), 315–322 (2018). https://doi.org/10.1109/TSM.2018.2825482
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