Deadlock analysis for a fault-tolerant system-Reference-Cited by-同舟云学术

Deadlock analysis for a fault-tolerant system

Published:1997 Issue: Volume: Page:60-74
ISSN:0302-9743
Container-title:Algebraic Methodology and Software Technology
language:
Short-container-title:

Author:

Buth Bettina,Kouvaras Michel,Peleska Jan,Shi Hui

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/BFb0000463

Reference13 articles.

1. N. A. Brock and D. M. Jackson: Formal Verification of a Fault Tolerant Computer. In Proceedings of 1992 Digital Avionics Systems Conference. (1992)

2. B. Buth and J. Peleska: Daimler-Benz Aerospace — Project DMS-R, FTC Development — Verification of Avionics Interface AVI. Technical Report, JP Software-Consulting, (1996).

3. B. Buth, J. Peleska and H. Shi: Daimler-Benz Aerospace — Project DMS-R, FTC Development — Fault Management Layer (FML): Verification of Deadlock Freedom. Technical Report, JP Software-Consulting, (1996).

4. Daimler-Benz Aerospace: DMS-R FTC Detailed Design Document Volume 3 (FML Software)

5. J. Davies: Specification and Proof in Real-Time CSP. Cambridge University Press (1993).

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