An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors-Reference-Cited by-同舟云学术

An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors

Published:1999 Issue: Volume: Page:1301-1311
ISSN:0302-9743
Container-title:Euro-Par’99 Parallel Processing
language:
Short-container-title:

Author:

Connors Daniel A.,August David I.,Crozier Kevin M.,Hwu andWen-mei W.,Puiatti Jean-Michel

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-48311-X_185

Reference10 articles.

1. J. Davidson and R. Vaughan. The effect of instruction set complexity on program size and memory performance. In Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, pages 60–64, October 1987.

2. S.A. Mahlke et al. Effective compiler support for predicated execution using the hyperblock. In Proceedings of the 25th International Symposium on Microarchitecture, pages 45–54, December 1992.

3. S.A. Mahlke et al. A comparison of full and partial predicated execution support for ILP processors. In Proceedings of the 22th International Symposium on Computer Architecture, pages 138–150, June 1995.

4. V. Kathail et al. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL-93-80, Hewlett-Packard Laboratories, Palo Alto, CA, February 1994.

5. W.W. Hwu et al. The Superblock: An effective technique for VLIW and superscalar compilation. The Journal of Supercomputing, 7(1):229–248, January 1993.

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design Principles for Synthesizable Processor Cores;Architecture of Computing Systems – ARCS 2012;2012

2. Value Prediction as a Cost-Effective Solution to Improve Embedded Processors Performance;Vector and Parallel Processing — VECPAR 2000;2001