Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Modelling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering
Reference28 articles.
1. Ayinala, M., Brown, M., & Parhi, K.K. (2012). Pipelined parallel FFT architectures via folding transformation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(6), 1068–1081.
2. Ayinala, M., Lao, Y., & Parhi, K.K. (2013). An in-place FFT architecture for real-valued signals. IEEE Transactions on Circuits and Systems II: Express Briefs, 60(10), 652–656.
3. Ayinala, M., & Parhi, K.K. (2013). FFT architectures for real-valued signals based on radix- 23 and radix- 24 algorithms. IEEE Transactions on Circuits and Systems I: Regular Papers, 60(9), 2422–2430.
4. Baas, B.M. (1999). A low-power, high-performance, 1024-point FFT processor. IEEE Journal of Solid-State Circuits, 34(3), 380–387.
5. Bergland, G.D. (1968). A fast Fourier transform algorithm using base 8 iterations. Mathematics of Computation, 22(102), 275–279.
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