The TaPaSCo Open-Source Toolflow
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Published:2021-05
Issue:5
Volume:93
Page:545-563
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ISSN:1939-8018
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Container-title:Journal of Signal Processing Systems
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language:en
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Short-container-title:J Sign Process Syst
Author:
Heinz CarstenORCID, Hofmann Jaco, Korinth Jens, Sommer Lukas, Weber Lukas, Koch Andreas
Abstract
AbstractThe integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Modelling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering
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1. PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04 2. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing;Design and Architecture for Signal and Image Processing;2023 3. Qilin;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30 4. Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs;2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES);2022-10 5. Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems;2022 32nd International Conference on Field-Programmable Logic and Applications (FPL);2022-08
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