Memory Controller for Vector Processor-Reference-Cited by-同舟云学术

Memory Controller for Vector Processor

Published:2016-12-28 Issue:11 Volume:90 Page:1533-1549
ISSN:1939-8018
Container-title:Journal of Signal Processing Systems
language:en
Short-container-title:J Sign Process Syst

Author:

Hussain Tassadaq,Palomar Oscar,Ünsal Osman S.,Cristal Adrian,Ayguadé Eduard

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering

Link

http://link.springer.com/article/10.1007/s11265-016-1215-5/fulltext.html

Reference34 articles.

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2. Espasa, R., Valero, M., & Smith, J.E. (1998). Vector architectures: past, present and future. In 12th international conference on Supercomputing.

3. Kozyrakism, C., & Patterson, D. (2003). Overcoming the limitations of conventional vector processors. In ACM SIGARCH Computer Architecture News.

4. Lee, Y., Avizienis, R., Bishara, A., Xia, R., Lockhart, D., Batten, C., & Asanović, K. (2011). Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators. In ACM SIGARCH Computer Architecture News, (Vol. 39 pp. 129–140): ACM.

5. Hussain, T., Pericas, M., Navarro, N., & Ayguade, E. Implementation of a Reverse Time Migration Kernel using the HCE High Level Synthesis Tool.

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