Author:
Imran Naveed,DeMara Ronald F.,Lee Jooheung,Huang Jian
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering
Reference61 articles.
1. Cho, H., Leem, L., Mitra, S. (2012). ERSA: error resilient system architecture for probabilistic applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(4), 546–558.
2. Karakonstantis, G., Mohapatra, D., Roy, K. (2012). Logic and memory design based on unequal error protection for voltage-scalable, robust and adaptive DSP systems. Journal of Signal Processing Systems (JSPS), 68, 415–431.
3. Whatmough, P.N., Das, S., Bull, D.M., Darwazeh, I. Circuit-level timing error tolerance for low-power dsp filters and transforms. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(6), 989–999.
4. Mitra, S., & McCluskey, E.J. (2000). Which concurrent error detection scheme to choose? In International test conference pp 985–994.
5. Mitra, S., Huang, W.J., Saxena, N.R., Yu, S.Y., McCluskey, E.J. (2004). Reconfigurable architecture for autonomous self-repair. IEEE Design Test of Computers, 21(3), 228–240.
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献