1. Agarwal, A., Hsu, S., Mathew, S., Anders, M., Kaul, H., Sheikh, F., Krishnamurthy, R. (2011). A 128x128b high-speed wide-AND match-line content addressable memory in 32nm CMOS. In 2011 Proceedings of the ESSCIRC (ESSCIRC) (pp. 83–86). doi: 1109/ESSCIRC.2011.6044920 .
2. Chang, YJ, & Lan, MF (2007). Two new techniques integrated for energy-efficient TLB design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(1), 13–23. doi: 1109/TVLSI.2006.887813 .
3. Chao, H. (2002). Next generation routers. Proceedings of the IEEE, 90(9), 1518–1558. doi: 1109/JPROC.2002.802001 .
4. Clark, L., & Chaudhary, V. (2010). Fast low power translation look aside buffers using hierarchical NAND match lines. In Proceedings of 2010 IEEE international symposium on circuits and systems (ISCAS) (pp. 3493–3496). doi: 1109/ISCAS.2010.5537832 .
5. Gripon, V., & Berrou, C. (2011). Sparse neural networks with large learning diversity. IEEE Transactions on Neural Networks, 22(7), 1087–1096. doi: 1109/TNN.2011.2146789 .