Area Efficient Sequential Decimal Fixed-point Multiplier
Author:
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering
Link
http://link.springer.com/content/pdf/10.1007/s11265-013-0795-6.pdf
Reference18 articles.
1. IEEE Standard for Floating-Point Arithmetic. IEEE working group of the microprocesser standards subcommittee (2008).
2. Cowlishaw, M. F. (2003). Decimal floating-point algorism for computers. In Proc. of the 16th IEEE symposium on computer arithmetic.
3. Cornea, M. et al. (2009). A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format. IEEE Transactions on Computers, 58(2), 148–162.
4. Wang, L.-K. et al. (2010). A survey of hardware designs for decimal arithmetic. IBM Journal of Research and Development, 54(2), 8:1–8:15.
5. Wang, L.-K. et al. (2007). Benchmarks and performance analysis of decimal floating-point applications. 25th International Conference on Computer Design (ICCD) (pp. 164–170).
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