A New Low Latency Parallel FIR Filter Scheme
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Information Systems,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s11265-005-4847-4.pdf
Reference9 articles.
1. T. Lin and H. Samueli, ?A 200-MHz CMOS x/sin(x) Digital Filter for Compensating D/A Converter Frequency Response Distortion,? IEEE Journal of Solid-State Circuits, vol. 26, no 9, 1991, pp. 1278?1285.
2. T. Yoshino, R. Jain, P. Yang, H. Davis, W. Gass, and A.H. Shah, ?A 100-MHz 64-Tap FIR Digital Filter in 0.8-? m BiCMOS Gate Array,? IEEE Journal of Solid-State Circuits, vol. 25, no 6, 1990, pp. 1494?1501.
3. H.-R. Lee, C.-W. Jen, and C.-M. Liu, ?A New Hardware Efficient Architecture for Programmable FIR Filters,? IEEE Trans. on Circuit and Systems-II, vol. 43, no. 9, 1996, pp. 637?644.
4. R.A. Hawley, B.C. Wong, T. Lin, J. Laskowski, and H. Samueli, ?Design Techniques for Silicon Compiler Implementations of High-Speed FIR Digital Filters,? IEEE Journal of Solid-State Circuits, vol. 31, no 5, 1996, pp. 656?667.
5. C.G. Caraiscos and K.Z. pekmestzi, ?Low-Latency Bit-Parallel Systolic VLSI Implementation of FIR Digital Filters,? IEEE Trans. on Circuits and Systems-II, vol. 43, no 7, 1996, pp. 1?7.
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