Author:
Ho H.,Szwarc V.,Kwasniewski T.
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Modelling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering
Reference28 articles.
1. Pasko, R., Schaumont, P., Derudder, V., Vernalde, V., & Durackova, D. (1999). A new algorithm for elimination of common subexpressions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(1), 58–68.
2. Macpherson, K. N., & Steward, R. W. (2006). Area efficient FIR filters for high speed FPGA implementation. IEE Proceeding: Vision, Image and Signal Processing, 153(6), 711–720.
3. Dempster, A. G., & Macleod, M. (1995). Use of minimum-adder multiplier blocks in FIR digital filters. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 42(9), 569–576.
4. Mirzaei, S., Hosangadi, A., & Kastner, R. (2006). FPGA implementation of high speed FIR filters using add and shift method. Proc. of the 14th Intl. Conference on FPGA FPGA'06, pp. 231–237.
5. Macleod, M. D., & Dempster, A. G. (2004). Common subexpression elimination algorithm for low-cost multiplierless implementation of matrix multipliers. Electronics Letters, 40(11), 651–652.
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献