Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications-Reference-Cited by-同舟云学术

Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications

Published:2008-07-12 Issue:1 Volume:56 Page:17-23
ISSN:1939-8018
Container-title:Journal of Signal Processing Systems
language:en
Short-container-title:J Sign Process Syst Sign Image Video Technol

Author:

Torres V.,Pérez-Pascual A.,Sansaloni T.,Valls J.

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering

Link

http://link.springer.com/content/pdf/10.1007/s11265-008-0252-0.pdf

Reference9 articles.

1. European Telecommunications Standards Institute. (1997). Digital video broadcasting (DVB): Framing structure, channel coding and modulation for 11/12 GHz satellite services. European standard (Telecommunications series), EN 300 421 V1.1.2.

2. Parhi, K. K. (1999). VLSI digital signal processing: design and implementation. New York: Wiley.

3. Gardner, F. M. (2005). Phaselock techniques. New York: Wiley.

4. Spagna, F. (2001) An improved delay compensation technique for digital clock recovery loops”. The 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol. 3, pp. 1395–1398.

5. Bergmans, J. W. M. (1995). Effect of loop delay on stability of discrete-time PLL. IEEE Transactions on Circuits and Systems-I, 42(4), 229–231, (April).

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