Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures-Reference-Cited by-同舟云学术

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Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures

Published:2010-03-17 Issue:3 Volume:62 Page:273-285
ISSN:1939-8018
Container-title:Journal of Signal Processing Systems
language:en
Short-container-title:J Sign Process Syst

Author:

Jung Yong-Kyu

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering

Link

http://link.springer.com/content/pdf/10.1007/s11265-010-0461-1.pdf

Reference33 articles.

1. Jerraya, A., Tenhunen, H., & Wolf, W. (2005). Multiprocessor systems-on-chips. IEEE Computer, 38(7), 36–40.

2. Jerraya, A., Petrot, F., & Bouchhima, A. (2006). Programming models and HW-SW interfaces abstraction for multi-processor SoC. IEEE Design automation conference, July 2006, pp. 280–285.

3. Martin, G. (2006). Overview of the MPSoC design challenge. IEEE Design automation conference, July 2006, pp. 274–279.

4. Zhaohui, L., Dickson, K., & McCanny, J. (2005). Application-specific instruction set processor for SoC implementation of modern signal processing algorithms. IEEE Transactions on Circuits and Systems, 52(4), 755–765.

5. Leibson, S., & Kim, J. (2005). Configurable processors: a new era in chip design. IEEE Computer, 38(7), 51–59.

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