Novel Shannon-Based Low-Power Full-Adder Architecture for Neural Network Applications
Author:
Publisher
Springer India
Link
http://link.springer.com/content/pdf/10.1007/978-81-322-1157-0_89
Reference4 articles.
1. Najm F (1994) A survey of power estimation techniques in VLSI circuits. IEEE Trans VLSI Syst 2:446–455
2. Lee JD, Yoony YJ, Leez KH, Park B-G (2001) Application of dynamic pass-transistor logic to an 8-bit multiplier. J Kor Phys Soc 38(3):220–223
3. Khatibzadeh A, Raahemifar K (2005) A novel design of a 6 GHz 8 × 8 bit pipelined multiplier, IEEE Proceedings of the 9th international database engineering and application symposium (IDEAS’25’05), pp 1–5
4. Nehru K, Shanmugam A, Deepa S Priyadarshini R (2010) A shannon based low power adder cell for neural network training. IACSIT Int J Eng Technol, 2(3)
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