Fast Multiplication with Partial Products Using Quaternary Signed Digit Number System

Author:

Hareesh P.,Kalyan Chakravathi Ch.,Rao D. Tirumala

Publisher

Springer India

Reference8 articles.

1. Vasundara Patel, K.S., Gurumurthy, K.S.: Design of high performance quaternary adders. Int. J. Comput. Theory Eng. 2(6), 944–952 (2010)

2. Moskal, J., Oruklu, E., Saniie, J.: Design and synthesis of a carry-free signed-digit decimal adder. In: IEEE International Symposium on Circuits and Systems, pp. 1089–1092 (2007)

3. Parhami, Behrooz: Carry-free addition of recoded binary signed-digit numbers. IEEE Trans. Comput. 37(11), 1470–1476 (1988)

4. Ahmed, J.U., Awwal, A.A.S.: Multiplier design using RBSD number system. In: Proceedings of the 1993 National Aerospace and Electronics Conference, vol. 1, pp. 180–184 (1993)

5. Dubey, S., Rani, R., Kumari, S., Sharma, N.: VLSI implementation of fast addition using quaternary signed digit number system. In: ICECCN, pp. 655–659 (2013)

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