1. Shi X, Imfeld K, Tanner S, Ansorge M. A low-jitter and low-power CMOS PLL for clock multiplication. Published in IEEE Esscirc—Mixed Signal, High Voltage & High Power Circuits 7, 2006.
2. Nanda U, Acharya DP, Patra SK. A new transmission gate cascode current mirror charge pump for fast locking low noise PLL. Circuits Systems and Signal Processing, © Springer Science Business Media New York, Apr. 2014.
3. Zhou J, Wang Z. A high-performance CMOS charge-pump for phase-locked loops. International conference on Microwave and millimeter wave technology ICMMT 2008, vol. 2, Apr 2008. pp. 839–842.
4. Zhiqun L, Shuangshuang Z, Ningbing H. Design of a high performance CMOS charge pump for phase-lockedloop synthesizers. J Semicond 14 February 2011;32(7):209–212.
5. Sujatha V, Dwahida banu RS. High performance charge pump phase locked loop with low current mismatch. IJCSI Jan 2012;9(Issue 1, N0. 2):442–446.