Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction-Reference-Cited by-同舟云学术

Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction

Published:2012-12-04 Issue: Volume: Page:89-100
ISSN:2194-5357
Container-title:Advances in Intelligent Systems and Computing
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Author:

Bhushan Sushil,Khandelwal Saurabh,Raj Balwinder

Publisher

Springer India

Link

http://link.springer.com/content/pdf/10.1007/978-81-322-1041-2_8.pdf

Reference15 articles.

1. Michael C. Wang. “Independent-Gate FinFET Circuit Design Methodology”. IAENG International Journal of Computer Science, 37:1, IJCS_37_1_06.

2. Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano, and Tomochika Harada, “A Self Controllable-Voltage-Level (SVL) Circuit for Low-Power, High-Speed CMOS Circuits” ESSCIRC 2002.

3. Nirmal, Vijaya Kumar , Sam Jabaraj. “NAND GATE USING FINFET FOR NANOSCALE TECHNOLOGY”. International Journal of Engineering Science and Technology Vol. 2(5), 2010, 1351-1358.

5. E. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong. “Device scaling limits of Si MOSFETs and their application dependencies”. Proc. IEEE, 89(3):259–288, (2001).

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