Author:
Chitti Sridevi,Chandrasekhar P.,Asharani M.,Krishnamurthy G.
Reference10 articles.
1. Chauhan, P., Clarke, E.M., Lu, Y., Wang, D.: Verifying IP core based system-on-chip designs. Carnegie Mellon University Research Showcase
2. Samanta, P., Chauhan, D., Deb, S., Gupta, P.K.: UVM based STBUS Verification IP for Verifying SOC Architectures. In: Proceedings of IEEE VLSI Design and Test, 18th International Symposium, doi:
10.1109/ISVDAT.2014.6881037
, Coimbatore, July 2014
3. Vaidya, B., Pithadiya, N.: An introduction to universal verification methodology. J. Inf. Knowl. Res. Electron. Commun. Eng. 2, Nov-12 to Oct-13
4. Assaf, M.H., Arima; Das, S.R., Hernias, W., Petriu, E.M.: Verification of ethernet IP core MAC design using deterministic test methodology. In: IEEE International Instrumentation and Mesurements Technology Conference, victoria, May 2008. doi:
10.1109/IMTC.2008.4547312
5. Tonfat, J., Reis, R.: Design and verification of a layer-2 ethernet MAC classification engine for a gGigabit ethernet switch. In: Proceedings of IEEE Electronics, Circuits, and Systems, Athens, Dec 2010. doi:
10.1109/ICECS.2010.5724475