An optimized parallel order scheme of the deblocking filtering process for enhancing the performance of the HEVC standard using GPUs-Reference-Cited by-同舟云学术

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An optimized parallel order scheme of the deblocking filtering process for enhancing the performance of the HEVC standard using GPUs

Published:2017-06-09 Issue:23 Volume:76 Page:24609-24634
ISSN:1380-7501
Container-title:Multimedia Tools and Applications
language:en
Short-container-title:Multimed Tools Appl

Author:

Fouad Mohamed M.,Dansereau Richard M.

Publisher

Springer Science and Business Media LLC

Subject

Computer Networks and Communications,Hardware and Architecture,Media Technology,Software

Link

http://link.springer.com/article/10.1007/s11042-017-4876-6/fulltext.html

Reference29 articles.

1. Bossen F (2011) Common test conditions and software reference configurations. Tech. Rep. Doc. JCTVC-l1100, San Jose CA

2. Bossen F, Bross B, Suhring K, Flynn D (2012) HEVC, complexity and implementation analysis. IEEE Trans Circuits Syst Video Technol 22(12):1685–1696

3. Chao YC, Lin JK, Yang JF, Liu BD (2006) A high throughput and data reuse architecture for H.264/AVC deblocking filter IEEE Asia pacific conference on circuits and systems, pp 1260–1263

4. Chi CC, Mesa MA, Juurlink B, Clare G, Henry F, Pateux S, Schierl T (2012) Parallel scalability and efficiency of HEVC parallelization approaches. IEEE Trans Circuits Syst Video Technol 22(12):1827–1838

5. Eldeken AF, Dansereau RM, Fouad MM, Salama GI (2015) High throughput parallel scheme for HEVC deblocking filter The 22 nd IEEE international conference on image processing, pp 1538–1542

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