Digit pipelined arithmetic on fine-grain array processors

Author:

Nagendra Chetana,Owens Robert Michael,Irwin Mary Jane

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Information Systems,Signal Processing

Reference28 articles.

1. K.E. Batcher, “Design of a Massively Parallel Processor,”IEEE Trans. on Computers, Vol. 29, pp. 836–840, 1980.

2. P. Bertin, D. Roncin, and J. Vuillemin, “Introduction to Programmable Active Memories,”Proc. of International Conference on Systolic Array Processors, pp. 301–309, 1989.

3. W.D. Hillis,The Connection Machine, Cambridge, MA: MIT Press, 1986.

4. J. Gray and T. Kean, “Configurable Hardware: A New Paradigm for Computation,”Advanced Research in VLSI, Proc. of the Decennial Caltech Conference on VLSI, pp. 1–17, 1989.

5. M.J. Irwin and R.M. Owens “A Micro-Grained VLSI Signal Processor,”ICASSP-92, pp. 641–644, 1992.

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An optimal time multiplication free algorithm for edge detection on a mesh;Journal of VLSI signal processing systems for signal, image and video technology;1996-08

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