Effects of Wafer Thinning Condition on the Roughness, Morphology and Fracture Strength of Silicon Die

Author:

McLellan Neil12,Fan Nelson12,Liu Shilai12,Lau Kim12,Wu Jingshen12

Affiliation:

1. Department of Package Development and Engineering, ASAT Ltd. Tsuen Wan, NT, Hong Kong

2. Department of Mechanical Engineering, Hong Kong University of Science & Technology, Kowloon, Hong Kong

Abstract

A systematic investigation on the effects of wafer thinning process on the surface roughness, morphology and fracture strength of silicon chips was conducted. The results of the study suggest that the fracture strength of the silicon chips was determined predominantly by the geometry and scratch tip sharpness of a few large and deep scratches formed during wafer thinning. Although additional polishing by dry-polishing technique after traditional mechanical coarse/fine grinding could greatly improve the average roughness of the die surface, it would not further strengthen the silicon chips because the dry polishing could not successfully remove large scratches or reduce the scratch size. Plasma etching was found to have a high effectiveness in fracture strength improvement. Mechanism study shows that plasma etching turned the very sharp and large scratches into U-grooves, leading to a reduced stress concentration, hence, a much improved fracture strength.

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Reference7 articles.

1. Lim, T. B., 1989, “The Impact of Wafer Back Surface Finish on Chip Strength,” IEEE/IRPS.

2. Landesberger, C., Klink, G., Schwinn, G., and Aschenbrenner, R., 2001, “New Dicing and Thinning Concept Improves Mechanical Reliability of Ultra Thin Silicon,” 2001 Int’l Symposium on Advanced Packaging Materials.

3. Savastiouk, S., Siniaguine, O., Reche, J., and Korczynski, E., 2000, “Thru-Silicon Interconnect Technology,” 2000 IEEE/CPMT Int’l Electronics Manufacturing Technology Symposium.

4. Siniaguine, O., 1998, “Atmospheric Downstream Plasma Etching of Si Wafers,” 1998 IEEE/CPMT Int’l Electronics Manufacturing Technology Symposium.

5. Veeco Metrology Group, 1999, “WYKO Surface Profilers Technical Reference Manual,” Version 2.2.1.

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