Fatigue of Chip Scale Package Interconnects Due to Cyclic Bending

Abstract

This study investigates the effect of quasi-static bending loads (strain rate=0.05/s) on the durability of 0.5 mm pitch Chip Scale Package (CSP) interconnects when assembled on FR4 substrates. The substrates have rows of CSPs and are subjected to three-point bending loads. Overstress curvature limits are experimentally determined and used to identify limits for zero-to-max cyclic bending loads. The test configuration is simulated using finite element modeling (FEM) and the total strain accumulated in the solder joints is estimated. Using the FEM model, a calibration curve is constructed to relate the cyclic curvature range in the substrate to the cyclic strain range in the critical solder joint. Bending moments along the substrate are estimated from the forces applied at the center of the board during the fatigue test. Strains measured on the substrate surface and the bending displacements measured at the center are used to estimate curvatures at different locations along the substrate. Using the calibration curve, the total strains in the solder joint are obtained for the applied loading. A strain-range fatigue damage model proposed by Coffin and Manson, is used to predict the cycles to failure for the applied loading. Predicted durability is compared to experimental measurements. Concave substrate curvature is found to be more damaging than convex curvature, for interconnect fatigue. Finite element simulations are repeated for life-cycle loading to predict acceleration factors. Using the acceleration factors, the product durability is estimated for life-cycle environments.