1. 1) See for example, http://www1.semi.org/en/node/57416
2. 2) G. E. Moore: "Cramming More Components Onto Integrated Circuits," Electronics, Vol. 38, pp. 114–117, 1965
3. 3) R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc: "Design of ion-implanted MOSFET's with very small physical dimensions," IEEE J. Solid-State Circuit, Vol. 9, pp. 256–268, 1974
4. 4) T. Ohba, Y. S. Kim, Y. Mizushima, N. Maeda, K. Fujimoto, and S. Kodama: "Review of Wafer-Level Three-Dimensional Integration (3DI) using Bumpless Interconnects for Tera-Scale Generation," IEICE Electron. Express, Vol. 12, pp. 1–14, 2015. https://doi.org/10.1587/elex.12.20150002
5. 5) D. S. Green: DARPA's CHIPS Program, and Making Heterogeneous Integration Common. In Proceedings of the 14th Annual Conference on 3D Architectures for Semiconductor Integration and Packaging (3D-ASIP), San Francisco, CA, USA, 5–7 December 2017. Available online: https://www.darpa.mil/news-events/2016-07-19