Design and Comparison of Constant Transconductance Architectures

Abstract

Constant transconductance (Gm) biasing circuits, as the name suggests, generate a bias current that ensures that the Gm of a MOS transistor remains constant. The Gm of a MOS transistor is a very important parameter as various other parameters of a circuit such as the gain, UGB (Unity Gain Bandwidth, poles, and zeros are strongly dependent upon it. Every analog circuit in a chip is subjected to varying PVT (Process, Voltage, and Temperature) conditions. This leads to a varying Gm of the devices, and hence the parameters such as the gain and UGB also tend to vary. Hence, constant Gm biasing is crucial in systems, where the parameters are expected to be constant regardless of the external factors. The majority of constant Gm biasing circuits make use of an external off-chip resistor. While this is a reasonable solution, it adds to the cost, area, and complexity of the solution. Hence, it is vital to model and design all the required functionalities within the chip, eliminating the requirement for any external components. In this paper, different architectures of constant Gm biasing circuits are designed and simulated in Cadence Virtuoso software. The proposed architecture has an error of 6.42% in the variation of transconductance, which is a significant improvement concerning the other architectures simulated. Additionally, the proposed architecture does not require any off-chip components while the other architectures require an off-chip resistor. Hence, the proposed solution has reduced cost and complexity.