Design of a Dynamic CMOS Incrementer/Decrementer and a Parallel Cascading Architecture

Abstract

Dynamic CMOS based transistor level designs of incrementer/decrementer circuit is presented in this work. The design of a new 8-bit decision module is first described. This is followed by elucidation of an original cascading architecture to realize larger size incrementer/decrementer circuits. From SPICE simulations corresponding to a 0.25μm CMOS process technology, it is inferred that an 8-bit incrementer/decrementer embedding the new decision module macro dissipates 48% less power for incrementing and 30% less power for decrementing than the one incorporating a conventional macro. Further, 16- bit and 32-bit incrementers/decrementers constructed using the proposed cascade consume 21% and 23% reduced average power for increment and decrement operations respectively than their conventional counterparts.