New Design Optimized and IC Area Efficient Rules for the Prevention of Plasma Processing Induced Damage on CMOS Circuit Reliability-Reference-Cited by-同舟云学术

New Design Optimized and IC Area Efficient Rules for the Prevention of Plasma Processing Induced Damage on CMOS Circuit Reliability

Published:2022-10-09 Issue: Volume: Page:
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Container-title:2022 IEEE International Integrated Reliability Workshop (IIRW)
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Author:

Martin Andreas¹,Schuler Bernd¹,Ankele Benno²,Nielen Heiko¹

Affiliation:

1. Infineon Technologies AG,Corporate Reliability Department,Neubiberg,Germany

2. Infineon Technologies Austria AG,Design-Technology Interface Group,Villach,Austria

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10032732/10032733/10032768.pdf?arnumber=10032768

Reference28 articles.

1. LEF/DEF Language Reference,2009

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3. A New Implementation Approach for Reliability Design Rules against Plasma Induced Charging Damage from Well Configurations of Complex ICs

4. A New Gate-Charging Protection Strategy for Transistors in Integrated-Circuit Test Chips and Products

5. Automated Test Structure Generation for Characterizing Plasma Induced Damage in MOSFET Devices;zwingman;Proc IEEE ICMTS (International Conference on Microelectronic Test Structures),2009

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